Crappy RISC-V CPU and fancy peripherals designed to be useful.

Quasi SoC

Crappy RISC-V CPU and fancy peripherals designed to be useful. Always half-baked. Prioritize compatibility over performance.

∂CPU (partial CPU)

• Multiple-cycle RISC-V RV32IM @ 62.5 MHz
• M-mode CSR (partial but enough)
• Interrupt (timer, external, software)
• Exception (ecall, break, partial invalid instructions)
• Basic/Custom memory protection, Sv32 MMU
• GDB debug over openocd JTAG
• Memory-mapped IO (1 host, multiple guests)
• Bus arbitration (multiple hosts, graphics unit or debugger)
• Formal verification (not planned)
• Pipeline (not planned)
• Supervisor/User privilege level support (not planned)

Peripherals

• ESP-PSRAM64H as main memory, 8 MB, QPI mode @ 62.5 M, burst R/W
• Cache, direct mapping 32 KB(configurable)
• SDRAM (Easy but not before I get a better board)
• GPIO (LEDs, buttons, switches)
• UART (921600 baud), load assembly from UART, reset CPU from UART
• SD card (SPI mode, SDHC)
• PS/2 keyboard
• HDMI character terminal
• HDMI frame buffer graphics, 320x240 8-bit color or 640x480 2-bit monochrome
• CH375 Serial, USB disk support
• W5500 ethernet module
• LAN8720 ethernet module w/ RGMII (Hard)
• ESP8266/ESP32 Wifi module (Boring)
• Interrupt Timer
• Bus converter to use AXI/Wishbone peripherals, high priority

Software

• Standard RISC-V toolchain for RV32IM Newlib
• Basic RISC-V tests passed
• CoreMark performance approx. 0.27 CoreMark/MHz
• MicroPython port, deprecated, TODO: update
• Fancy but very slow soft renderer

Boards & FPGAs

• xc7z010 PL @ SqueakyBoard, main dev platform ref
• xc7z020 PL @ PYNQ-Z1 w/ extension PMOD module ref
• xc7k325t @ Memblaze PBlaze 3 w/ extension board ref
• xc6slx16 @ Nameless LED controller module, UART only
• ep2c35 @ Cisco HWIC-3G-CDMA router module ref, plan to buy
• Xilinx 7-series w/ free software toolchain(Symbiflow), high priority
• lfe5u or iCE40 w/ free software toolchain(Symbiflow, icestorm)
• K210 or some other hardcore RISCV

Build & Run

Instructions here

Gallery

Pingo soft renderer of Viking room, with testing color strips, on HDMI monitor.

Ported MicroPython, on HDMI monitor.

CoreMark benchmarking, serial port.

Process switching demo and inter-process communication, early-stage microkernel osdev, serial port.

Credits

Many peripherals' code are based on other's work. If I miss something please point out.

HDMI module, modified

HDMI module

SD card module, modified

UART module, heavily modified

Computer Organization and Design, where everything started

License

GPL-V3 except sd_controller.v