Ara
Ara is a vector unit working as a coprocessor for the CVA6 core. It supports the RISC-V Vector Extension, version 0.9.
Dependencies
Check DEPENDENCIES.md for a list of hardware and software dependencies of Ara.
Supported instructions
Check FUNCTIONALITIES.md to check which instructions are currently support by Ara.
Get started
Make sure you clone this repository recursively to get all the necessary submodules:
git submodule update --init --recursive
If the repository path of any submodule changes, run the following command to change your submodule's pointer to the remote repository:
git submodule sync --recursive
Toolchain
Ara requires a RISC-V GCC toolchain capable of understanding the vector extension, version 0.9.x.
To build this toolchain, run the following command in the project's root directory.
# Build the GCC toolchain
make toolchain
Verilator
Ara requires an updated version of Verilator, for RTL simulations.
To build it, run the following command in the project's root directory.
# Build Verilator
make verilator
Configuration
Ara's parameters are centralized in the config folder, in the config.mk file. Please check config/README.md for more details.
Software
Build Applications
The apps folder contains example applications that work on Ara. Run the following command to build an application. E.g., hello_world:
cd apps
make bin/hello_world
RISC-V Tests
The apps folder also contains the RISC-V tests repository, including a few unit tests for the vector instructions. Run the following command to build the unit tests:
cd apps
make riscv_tests
RTL Simulation
To simulate the Ara system with ModelSim, go to the hardware folder, which contains all the SystemVerilog files. Use the following command to run your simulation:
# Go to the hardware folder
cd hardware
# Apply the patches (only need to run this once)
make apply-patches
# Only compile the hardware without running the simulation.
make build
# Run the simulation with the *hello_world* binary loaded
app=hello_world make sim
# Run the simulation with the *some_binary* binary. This allows specifying the full path to the binary
preload=/some_path/some_binary make sim
# Run the simulation without starting the gui
app=hello_world make simc
It is also possible to simulate the unit tests compiled in the apps folder. Given the number of unit tests, we use Verilator. Use the following command to install Verilator, verilate the design, and run the simulation:
# Go to the hardware folder
cd hardware
# Apply the patches (only need to run this once)
make apply-patches
# Verilate the design
make verilate
# Run the tests
make riscv_tests_simv
Alternatively, you can also use the riscv_tests target at Ara's top-level Makefile to both compile the RISC-V tests and run their simulation.
Publication
If you want to use Ara, you can cite us:
@Article{Ara2020,
author = {Matheus Cavalcante and Fabian Schuiki and Florian Zaruba and Michael Schaffner and Luca Benini},
journal= {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
title = {Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI},
year = {2020},
volume = {28},
number = {2},
pages = {530-543},
doi = {10.1109/TVLSI.2019.2950087}
}
![[HW] Add support for vector fixed-point instructions](https://avatars.githubusercontent.com/u/91871447?v=4)
![[HW] Adding support for Fixed-Point vector instructions](https://avatars.githubusercontent.com/u/6366236?v=4)
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