OSH Park and Aisler can’t process the Gerber files propers because they report a missing outline. JLC PCB doesn’t have any problems with the files, though.

Hey, thought this would be a neat project to include over on kitspace.org. All that's required is to add a kitspace.yml pointing at the right BOM. If you are happy to add it, simply merge this and I'll put it up. The page will continue to update with this repo as you make changes (thought the delay can be up to 24hrs).

Here is a preview of what it will look like. The BOM could be improved a little, especially to add distributor numbers for the "Buy Parts" buttons to show up. I do have a project to help with that: bom-builder (more info). If you would like free access to a hosted version of that, shoot me an email: [email protected]

Because of the limitation of the jlcpcb production process, the minimum drilling hole diameter is 0.2mm, but the drilling hole diameter used in the two drilling files TX1 and TX2 is 0.102mm, so it may not be approved.

There are small typos in:

• hardware/README.md
• software/libcariboulite/src/caribou_smi/caribou_smi.c
• software/libcariboulite/src/caribou_smi/ref/rpi_dma_test.c
• software/libcariboulite/src/caribou_smi/ref/rpi_dma_utils.h
• software/libcariboulite/src/caribou_smi/register_utils.h
• software/libcariboulite/src/io_utils/pigpio/command.c
• software/libcariboulite/src/io_utils/pigpio/command.h
• software/libcariboulite/src/io_utils/pigpio/pigpio.c
• software/libcariboulite/src/io_utils/pigpio/pigpio.h

Fixes:

• Should read believe rather than belive.
• Should read uncached rather than unchached.
• Should read control rather than contol.
• Should read uncached rather than unchahced.
• Should read terminated rather than teminated.
• Should read substantial rather than substancial.
• Should read presumably rather than presumablly.

Semi-automated pull request generated by https://github.com/timgates42/meticulous/blob/master/docs/NOTE.md

Hi,

would like to know if you plan to share the project pcb file (in kicad would be great).

I would like modify the design to make a more simple and cheapest project to evaluate the AT86RF215(maybe put more than one in one pcb or make them stackable for multiple channels) with the raspberry pi and most of the RF mixer part is not needed.

P.D.

From your bom the MAAM-011206-TR1000 RF amplifier is obsolete and the replace part MAAM-011206-TR3000 cost 11 euros in mouser and you use 2!! and total bom is almost 100€ on mouser(the best place i found they have all components).

Thanks, your project is very promising, I hope you can make it to buy one.

Hi, based on specifications ADS-B (1090 MHz) should be slightly outside CaribouLite ISM frequency range (1020 MHz max). But I also read that frequency ranges are somewhat conservative. Is the maximum tunable frequency of 1020 MHz a hardware limit in the sense that the modem can't be tuned at 1090 MHz? Or it will be some kind of software-based limit? So overall the question is if I could be able to receive ADS-B (1090 MHz) signals with CaribouLite ISM version, thank you.

Hi @meexmachina ,

Lately, I have been reviewing your new SMI kernel modules and if I understand well you are restarting SMI and DMA transfers as soon as you copied samples into kfifo. So, I am wondering how you could avoid 100% of loss because this restart process (SMI and DMA) occurs in DMA ISR (and this ISR may have some significant latency depending on system load and this latency could be large enough to fill up the FPGA fifos ending up in samples loss.

I have confirmed the above assumptions with a home made test bench using your drivers stressing a bit the system to simulate a decent user land application. From time to time I noticed some loss (more or less severe depending on the load). To detect such loss, I had to implement a transport protocol including sequence numbering and CRC otherwise it could be pretty difficult to detect some issues.

So my questions are as follows:

1. Do you still rely on DMA ISR to restart the whole SMI/DMA process?
2. Do you experience samples loss when stressing the system?
3. Did you find a way to configure SMI for endless transfer - one start, infinite length -?

First of all, many thanks for your contribution! This is a great foundation for tailor made SDR design. So, I could not wait for your delivery so I decided to review and play with your design (using verilog simulation first and lately using a home made board).

Back to the issue, it seems you have built your own asynchronous FIFO from dual_clock_fifo module which looks suitable and you get rid of graycode handling (which is commonly used to address metastablity issues). Is there a reason for that?

Furthermore, it seems that you should take into account address width when your compute full_o and empty_o, otherwise you may have overflow issues

basically, I would expect something like full_o <= ((wr_addr + 2) & ((2**ADDR_WIDTH)-1)) == rd_addr; instead of full_o <= (wr_addr + 2) == rd_addr;

https://github.com/cariboulabs/cariboulite/blob/main/firmware/complex_fifo.v#L30 https://github.com/cariboulabs/cariboulite/blob/main/firmware/complex_fifo.v#L34 https://github.com/cariboulabs/cariboulite/blob/main/firmware/complex_fifo.v#L49

Hi, Im looking forward to use this compact TRX SDR. By the way, caribou lite can be controlled by Jetson? If so , Jetson use GPGPU can process much IQ signals faster.

Hi, I stumbled across your impressive project. Do you plan on adding something like U.FL sockets on J1/J3 of the RF switch (U11) to bypass it in cases where a user wants a dedicated rx and tx connector for bands higher than 1GHz? Using a 0 ohm resistor one could choose between the different options? Regards